1. Field of the Invention
The present invention relates to a method and related apparatus for performing frequency division, and more particularly, to a method and related apparatus for performing non-integer frequency division and for simplifying a logic circuit.
2. Description of the Prior Art
In modern information society, files, statistics, and video data can be speedily transmitted, processed, and stored by electronic signals. Electronic circuits (especially digital electronic circuits) for processing electronic signals become an important base of hardware. In an electronic circuit, it is necessary to integrate many circuits with different functions. In order to coordinate the operations of different circuits, each circuit must be triggered by a steady clock. Due to the complexity of electronic systems, this requires clocks with different frequencies to trigger different circuits. For instance, in a microprocessor, operational circuits for processing data and memory circuits for storing data work under clocks with different frequencies, and require triggering by clocks with different frequencies. Therefore manufactures design electronic circuits for the requirements of multiple-clock systems.
Please refer to FIG. 1. FIG. 1 shows functions of a typical phase-locked circuit 10. The phase-locked circuit 10 generates an output clock CPo1 according to a standard clock CPr for triggering other circuits. The phase-locked circuit 10 comprises a phase/frequency difference detector 14, a low-pass filter 16, a voltage-controlled oscillator 18, a 1/Np frequency dividor 12A, and a 1/Mp frequency dividor 12B. The standard clock CPr divided by the frequency dividor 12A becomes a clock CPa, the period of CPa being Np times the period of CPr. In the same way, the output clock CPo1 from the voltage-controlled oscillator 18 divided by the frequency dividor 12B becomes a clock CPb, the period of CPb being Mp times the period of CPo1. The detector 14 detects the phase/frequency difference between CPa and CPb, and inputs the result into the filter 16. According to the result, the filter 16 generates the corresponding control voltage Vcp for controlling the voltage control oscillator 18 to regulate the frequency of Cpo1. Since the clock CPb changes with CPo1, the phase/frequency difference between clock CPa and regulated clock CPb is detected again by the detector 14. As the loop among the detector 14, the filter 16, and the voltage-controlled oscillator 18 operate, the frequency/phase of CPb locked will be locked as the same as that of CPa. Then the clock CPo1 generated by the voltage-controlled oscillator 18 can be used to trigger other circuits (not shown in FIG. 1). Due to the operations of 12A and 12B, the period of CPo1 is (Np/Mp) times the period of the standard clock CPr.
Please refer to FIG. 2. FIG. 2 is an illustration of the voltage-controlled oscillator 18 in FIG. 1. The voltage-controlled oscillator 18 (also known as a chain oscillator) is formed by a plurality of differential inverters 20 connected together. As an example, the illustration in FIG. 2 only shows two inverters 20. In FIG. 2, the first inverter 20 outputs two clocks with opposite phases C2 and C4 and inputs them into the second inverter 20. The outputs C1 and C3 of the second inverter 20 are routed back to the first inverter 20. Please refer to FIG. 3 and FIG. 2. FIG. 3 shows timing states of C1 to C4 while the voltage-controlled oscillator 18 is working. The vertical axis shows wave amplitude and the horizontal axis shows time. As shown in FIG. 3, the clocks C1 and C3 with opposite phases rise from level L to level H and drop from level H to level L at tp0, respectively. After the first inverter receives the level adjustment of C1 and C3 at tp0, the first inverter will wait for a delay Td, and invert the outputs C2 and C4 to level L and level H at tp1, respectively. After the level adjustment of C2 and C4 at tp1 lasting for a delay Td, the level adjustment of C1 and C3 occurs at tp2. Repeated in the same way, four clocks C1 to C4 with the same period Tp will be formed, with Tp being four times the period of Td. The inverters 20 of the voltage-controlled oscillator 18 can receive a control voltage Vcp to change the delay Td for modifying the periods of C1 to C4. One of clocks C1 to C4 can be an output clock Cpo1 of the voltage control oscillator 18.
As shown in FIG. 3, the periods of C1 and C4 are the same as Tp, and the phases are different. Regarding the situation, please refer to FIG. 4. FIG. 4 shows, similar to FIG. 3, states of clocks C1 to C4. Clearly seen in FIG. 4, the phases of C1 to C4 are uniformly distributed over 360 degrees, that is to say, the phase difference is 90 degrees (a quarter of Tp). In other words, the oscillator 18 can generate many clocks with phases uniformly distributed in a period.
As mentioned above, electronic circuits require many different clocks to trigger different circuits. However, the phase-locked circuit 10 in FIG. 1 only can generate an output clock Cpo1 to trigger circuits. In the prior art, when many clocks with different frequencies (especially non-integer frequencies) are required, the required output clocks must be respectively generated by many phase-locked circuits. Regarding this situation, please refer to FIG. 5. FIG. 5 is a diagram of a prior art signal circuit 22 for generating two clocks CPo1 and CPo2. In order to generate two output clocks, the signal circuit 22 not only generates an output clock CPo1 by the phase-locked circuit 10 in FIG. 1, but also generates the other output clock CPo2 by another identical phase-locked circuit 24. As phase-locked circuits require analog circuits (such as filters and voltage-controlled oscillators), the layout of a phase-locked circuit is large. If a plurality of phase-locked circuits are used for generating many output clocks, the size of layout must be larger. This increases the cost, the size of layout, and power consumption.